The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2026
Filed:
Dec. 30, 2022
Intel Corporation, Santa Clara, CA (US);
Chunhui Mei, San Diego, CA (US);
Jiasheng Chen, El Dorado Hills, CA (US);
Ben J. Ashbaugh, Folsom, CA (US);
Fangwen Fu, Folsom, CA (US);
Hong Jiang, Los Altos, CA (US);
Guei-Yuan Lueh, San Jose, CA (US);
Rama S.B. Harihara, Santa Clara, CA (US);
Maxim Kazakov, San Diego, CA (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
A scalable and configurable clustered systolic array is described. An example of apparatus includes a cluster including multiple cores; and a cache memory coupled with the cluster, wherein each core includes multiple processing resources, a memory coupled with the plurality of processing resources, a systolic array coupled with the memory, and one or more interconnects with one or more other cores of the plurality of cores; and wherein the systolic arrays of the cores are configurable by the apparatus to form a logically combined systolic array for processing of an operation by a cooperative group of threads running on one or more of the plurality of cores in the cluster.