The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2026
Filed:
Jun. 03, 2022
Intel Corporation, Santa Clara, CA (US);
Vikram B. Suresh, Portland, OR (US);
Sanu K. Mathew, Portland, OR (US);
Christopher Schaef, Hillsboro, OR (US);
Chandra S. Katta, Cupertino, CA (US);
Long Sheng, Shanghai, CN;
Chin S. Park, Palo Alto, CA (US);
Srinivasan Rajagopalan, Palo Alto, CA (US);
Raju Rakha, Santa Clara, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments herein relate to optimizing the operation of multiple integrated circuits (ICs) operating in parallel. In one aspect, the ICs are arranged in a voltage-stacked configuration, and an operating frequency of each IC is controlled using a tunable replica circuit to stabilize its voltage drop. The tunable replica circuit mimics a critical path on the IC. In another aspect, an IC is divided into top and bottom portions which are in respective voltage domains on a substrate. The substrate include a deep n-well region for the higher voltage domain. In another aspect, a physically unclonable function (PUF) is used to generate identifiers for each IC among a multiple ICs on a board. Entropy sources of the PUF generate bits of the identifiers. Unstable entropy sources are identified and their bits are masked out.