The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2026
Filed:
May. 11, 2022
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Yangyang Sun, San Diego, CA (US);
Srikanth Kulkarni, Dublin, CA (US);
Lily Zhao, San Diego, CA (US);
Milind Shah, San Diego, CA (US);
Assignee:
QUALCOMM INCORPORATED, San Diego, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/69 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/095 (2026.01); H10W 70/611 (2026.01); H10W 70/69 (2026.01); H10W 74/114 (2026.01); H10W 74/121 (2026.01); H10W 90/00 (2026.01); H10W 74/15 (2026.01); H10W 90/401 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract
A package comprising a substrate comprising a first surface and a second surface; a first integrated device coupled to the first surface of the substrate; an interconnection die coupled to the first surface of the substrate; a first encapsulation layer coupled to the first surface of the substrate, wherein the first encapsulation layer encapsulates the first integrated device and the interconnection die; and a second integrated device coupled to the second surface of the substrate.