The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

May. 01, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Su-Chun Yang, Hsinchu, TW;

Jui Hsuan Tsai, Taipei, TW;

Chiao-Chun Chang, Hsinchu, TW;

Chu-Chuan Huang, Hsinchu, TW;

Jih-Churng Twu, Hsinchu, TW;

Chung-Shi Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H10W 70/60 (2026.01); H10W 70/685 (2026.01); H10W 72/00 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/611 (2026.01); H10W 70/685 (2026.01); H10W 72/0198 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/794 (2026.01);
Abstract

A process includes depositing an edge fill dielectric over a first workpiece and a device disposed thereon. The edge fill dielectric is patterned so that only the edge portions remain. A second dielectric material is formed over the first workpiece, device, and edge fill dielectric. A planarization process levels the second dielectric material and the device. A bonding layer is formed thereon and a second workpiece bonded thereto by a dielectric-to-dielectric bond.


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