The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Jun. 27, 2023
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Alain F. Loiseau, Williston, VT (US);

Romain H.A. Feuillette, Williston, VT (US);

Mujahid Muhammad, Essex Junction, VT (US);

Peter T. Coutu, Williston, VT (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 46/00 (2026.01); G01R 31/28 (2006.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10W 46/00 (2026.01); G01R 31/2887 (2013.01); H10W 20/42 (2026.01); H10W 46/106 (2026.01);
Abstract

An integrated circuit (IC) includes a plurality of metal layers, and a machine-readable code in a selected metal layer of the plurality of metal layers. A wafer includes a plurality of the ICs. An IC wafer testing system includes a scanner configured to read the machine-readable code in the metal layer of the IC in the wafer, and a tester configured to perform testing on the IC in the wafer based on testing information obtained from storage based on the machine-readable code. A method may include forming the IC including a plurality of metal layers and forming a selected metal layer of the IC including the machine-readable code in metal in the selected metal layer. The method may further include testing the IC. The machine-readable code reduces the complexity and time needed to setup and test an IC in a wafer.


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