The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Mar. 20, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tsung-Han Tsai, Kaohsiung City, TW;

Pin Chun Shen, Changhua County, TW;

Ta-Chun Lin, Hsinchu, TW;

Chun-Sheng Liang, Changhua County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/43 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/43 (2025.01); H10D 30/014 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01);
Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes first semiconductor channel layers, second semiconductor channel layers, a dielectric wall, a gate structure, a source/drain electrode and an inner spacer. The first semiconductor channel layers are stacked vertically apart along a first direction over a substrate. The second semiconductor channel layers are stacked vertically apart along the first direction over the substrate. The dielectric wall is disposed between and separates the first semiconductor channel layers and the second first semiconductor channel layers, wherein the dielectric wall comprises a liner and a dielectric wall material disposed over the liner. The gate structure extends along a second direction perpendicular to the first direction disposed crossing over a channel region of the first fin structure and a channel region of the second fin structure. The source/drain electrode is in contact with the first semiconductor channel layers. The inner spacer is enclosed by the first semiconductor channel layers, the gate structure, the dielectric wall and the source/drain electrode, wherein the inner spacer is in contact with the dielectric wall material of the dielectric wall.


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