The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Sep. 01, 2022
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Prantik Mahajan, Dresden, DE;

Ajay, Aligarh, IN;

Souvick Mitra, Essex Junction, VT (US);

Robert J. Gauthier, Williston, VT (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 18/00 (2025.01); H10D 62/10 (2025.01); H10D 84/00 (2025.01);
U.S. Cl.
CPC ...
H10D 18/241 (2025.01); H10D 18/251 (2025.01); H10D 62/126 (2025.01); H10D 84/138 (2025.01); H10D 62/116 (2025.01);
Abstract

Device structures including a silicon-controlled rectifier and methods of forming a device structure including a silicon-controlled rectifier. The device structure comprises a first well and a second well in a semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well and the second doped region have a first conductivity type, and the second well and the first doped region have a second conductivity type opposite from the first conductivity type. The second well adjoins the first well along an interface. A third doped region includes a first portion in the first well and a second portion in the second well, and a gate structure that overlaps with a portion of the second well.


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