The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

May. 30, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chun-Chieh Lu, Taipei City, TW;

Han-Jong Chia, Hsinchu City, TW;

Sai-Hooi Yeong, Zhubei City, TW;

Bo-Feng Young, Taipei, TW;

Yu-Ming Lin, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/30 (2023.01); H10B 51/20 (2023.01); H10D 30/67 (2025.01); H10D 99/00 (2025.01);
U.S. Cl.
CPC ...
H10B 51/30 (2023.02); H10B 51/20 (2023.02); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 99/00 (2025.01);
Abstract

Provided is a ferroelectric memory device having a dielectric layer vertically interleaved between a first conductive line and a second conductive line. A first ferroelectric portion is arranged along a sidewall of the first conductive line and a second ferroelectric portion is arranged along a sidewall of the second conductive line. A channel layer is arranged along sides of the dielectric layer, the first conductive line, and the second conductive line. A topmost surface of the first ferroelectric portion is vertically separated from a bottommost surface of the second ferroelectric portion by the channel layer.


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