Semiconductor memory device with processing-in-memory using test circuitry

Abstract

Disclosed are methods, systems, and apparatuses for a memory device with test circuitry-based processing-in-memory (PIM). The memory device utilizes circuitry used to control, sequence, and/or perform test functions, found on a die of the memory device (e.g., an interface die and/or memory die), to perform PIM functions. For example, the memory device may utilize a memory built-in self-test (mBIST) automatic pattern generator (APG) for PIM sequencing. To control PIM operations, the mBIST APG may fetch and decode microcode instructions local to the die. The microcode instructions may be fetched from a read-only memory (ROM) and/or non-volatile memory. Microcode instructions to perform desired PIM operations may be written to the non-volatile memory by a host device coupled to the memory device.