The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Jul. 29, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Umberto Di Vincenzo, Capriate San Gervasio, IT;

Ferdinando Bedeschi, Biassono, IT;

Paolo Fantini, Vimercate, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 13/0069 (2013.01); G11C 2013/0083 (2013.01); G11C 2213/71 (2013.01);
Abstract

Methods, systems, and devices for a sensing circuit in a vertical memory system are described. An apparatus may include a set of memory cells each coupled with a respective pillar of a set of pillars. A set of transistors, each of which is coupled with a digit line common to the set of memory cells, may be coupled with a respective pillar of the set of pillars. A first transistor of the set of transistors may include a first terminal coupled with a first bias line and a first pillar of the set of pillars, and may include a second terminal coupled with the digit line. A second transistor of the set of transistors may include a first terminal coupled with a second bias line and a second pillar of the set of pillars, and may include a gate terminal coupled with the digit line.


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