Method of fin selection for improved performance in semiconductor devices

Abstract

A method includes receiving an integrated circuit (IC) design layout that includes a design boundary and a pair of design fin patterns having a fin spacing and a fin pitch. The method further includes creating a mandrel mask pattern, which includes determining an edge of the mandrel mask pattern based on a location of the design boundary, the fin spacing, and the fin pitch, and determining a width of the mandrel mask pattern based on the fin spacing and the fin pitch. The method further includes creating a cut mask pattern based on the mandrel mask pattern and the design fin patterns, wherein the cut mask pattern is configured to protect an area of a semiconductor wafer corresponding to the design fin patterns. The method further includes fabricating a mandrel mask having the mandrel mask pattern and fabricating a cut mask having the cut mask pattern.