The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2026

Filed:

Mar. 18, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Qiang Yu, Saratoga, CA (US);

Gwang-Soo Kim, Portland, OR (US);

Said Rami, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 1/20 (2025.01); H10W 20/40 (2026.01); H10W 90/00 (2026.01); H10W 72/90 (2026.01); H10W 80/00 (2026.01);
U.S. Cl.
CPC ...
H10D 1/20 (2025.01); H10W 20/497 (2026.01); H10W 90/00 (2026.01); H10W 72/926 (2026.01); H10W 72/936 (2026.01); H10W 72/9445 (2026.01); H10W 80/701 (2026.01); H10W 90/792 (2026.01);
Abstract

In one embodiment, an apparatus includes a first integrated circuit die with metal bonding pads that are co-planar with an external surface of the die and a second integrated circuit die with metal bonding pads that are co-planar with an external surface of the die. The first and second integrated circuit dies are coupled together such that their external surfaces are in contact and the metal pads of the first integrated circuit die are in direct contact with respective metal pads of the second integrated circuit die. The apparatus also includes an inductor formed at least partially by the metal pads of the first integrated circuit die and the metal pads of the second integrated circuit die.


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