Apparatuses and methods for delay-locked loop clock control

Abstract

An example apparatus includes a clock input circuit to provide an internal clock signal based on an external clock signal, and a command decoder configured to provide a command signal based on a received command. The example apparatus further includes an internal clock generator having DLL circuit to receive the internal clock signal and the command signal and to provide a phase-adjusted internal clock signal based on the internal clock signal. In response to receipt of the command signal, the DLL circuit enables provision of the phase-adjusted internal clock signal to an input/output circuit and stops provision of the phase-adjusted internal clock signal after a count of clock cycles of the internal clock signal exceeds a predetermined count value. The predetermined count value is based on a signal propagation time of the internal clock signal from the output of the internal clock circuit to an output of the input/output circuit.