The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2026
Filed:
Oct. 07, 2024
Eliyan Corporation, Santa Clara, CA (US);
Curtis Mcallister, Los Altos, CA (US);
Paul Hylander, Bellevue, WA (US);
Ramin Farjadrad, Los Altos, CA (US);
Syrus Ziai, Los ALtos, CA (US);
Eliyan Corp., Santa Clara, CA (US);
Abstract
A memory chiplet includes storage and multiple memory control circuits. Each of the multiple memory control circuits to control a memory access operation to the storage. Multiple channel circuits are employed in the memory chiplet to transfer channel data between the multiple memory control circuits and the storage at a channel bandwidth. Multiple link input/output (I/O) circuits couple the memory chiplet to a host integrated circuit (IC) chiplet. Each of the multiple link I/O circuits transfer link data at a link bandwidth that is free to be different than the channel bandwidth. Bandwidth balancing circuitry, based on relative values between the channel bandwidth and the link bandwidth, selectively configures the multiple channels to transfer a total amount of data at a fully-available link bandwidth of the multiple links or selectively configure the multiple links to transfer the total amount of data at a fully-available channel bandwidth of the multiple channels.