The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Aug. 23, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Zi-Jheng Liu, Taoyuan City, TW;

Ting-Yang Yu, Hsinchu, TW;

Ming-Tan Lee, Kaohsiung City, TW;

Hung-Jui Kuo, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49894 (2013.01); H01L 24/08 (2013.01); H01L 25/16 (2013.01); H01L 2224/08235 (2013.01); H01L 2924/37001 (2013.01);
Abstract

A semiconductor package includes a first die, a second die and a redistribution layer structure. The first die and the second die are disposed laterally. The redistribution layer structure is disposed over and electrically connected to the first die and the second die, wherein the redistribution layer structure includes a plurality of vias and a plurality of lines stacked alternately and electrically connected to each other and embedded by a plurality of polymer layers, and wherein from a top view, first vias of the plurality of vias overlapping with the first die or the second die have an elliptical-like shape.


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