The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

May. 11, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Yun Cheng, Hsinchu City, TW;

I-Ming Chang, ShinChu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 64/017 (2025.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01);
Abstract

A method for forming a semiconductor device structure includes forming a fin structure over a substrate. The method also includes forming a dummy gate structure across the fin structure. The method also includes depositing a spacer layer over the fin structure and the dummy gate structure. The method also includes implanting dopants into the spacer layer to form a first doped region vertically overlapping the dummy gate structure and a second doped region over the fin structure without vertically overlapping the dummy gate structure. A middle region of the spacer layer connects the first doped region and the second doped region. The method also includes removing the first doped region and the second doped region of the spacer layer. The method also includes forming a source/drain structure attached to the fin structure after removing the first doped region and the second doped region of the spacer layer.


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