The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Jan. 01, 2024
Applicant:

Powertech Technology Inc., Hsinchu County, TW;

Inventors:

Shang-Yu Chang Chien, Hsinchu County, TW;

Nan-Chun Lin, Hsinchu County, TW;

Assignee:

POWERTECH TECHNOLOGY INC., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 20/20 (2026.01); H10W 70/60 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 72/00 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 20/20 (2026.01); H10W 70/611 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 74/114 (2026.01); H10W 90/701 (2026.01); H10W 90/734 (2026.01); H10W 72/073 (2026.01); H10W 90/724 (2026.01);
Abstract

A package structure and a manufacturing method thereof are provided. The package structure includes a first package including a first redistribution layer, at least one chip and a second redistribution layer, and at least one second package disposed on the first package and including a substrate, an adhesive layer, at least two optical chips, an encapsulant layer, and a third redistribution layer. The optical chips are attached to a surface of the substrate close to the first package through the adhesive layer, and each optical chip has an optical surface close to the substrate. The encapsulant layer is disposed on the surface and surrounds the optical chips. The third redistribution layer is disposed between the encapsulant layer and the second redistribution layer, in which the second redistribution layer is electrically connected to the optical chips through the third redistribution layer.


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