Device scaling by isolation enhancement

Abstract

A device includes a gate electrode and a gate dielectric surrounding the gate electrode. The gate electrode surrounds a nanostructure. The nanostructure includes stacked nanosheets. The gate dielectric is formed by a high-k (HK) material. The HK material covers sidewalls of the gate electrode in a direction aligned to adjacent devices. Portions of the HK material are recessed from the sidewalls and refilled by a dielectric material with a dielectric constant less than the HK material and an electrical isolation capability greater than the HK material. Replacing the HK material over the sidewalls of the gate electrode with the dielectric material enhances electrical isolation between the gate electrode with adjacent contacts. Consequently, it can reduce electrical leakage between metal gate (MG) contacts and metal-to-device (MD) contacts in scaled transistors of an integrated circuit (IC).