The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Jul. 11, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Takashi Ando, Eastchester, NY (US);

Alexander Reznicek, Troy, NY (US);

Pouya Hashemi, Purchase, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H10D 30/00 (2025.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 64/68 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10W 20/00 (2026.01);
U.S. Cl.
CPC ...
H10D 30/62 (2025.01); H10D 30/019 (2025.01); H10D 30/0191 (2025.01); H10D 30/0193 (2025.01); H10D 30/0194 (2025.01); H10D 30/0195 (2025.01); H10D 30/0196 (2025.01); H10D 30/0197 (2025.01); H10D 30/0198 (2025.01); H10D 30/024 (2025.01); H10D 30/501 (2025.01); H10D 30/502 (2025.01); H10D 30/503 (2025.01); H10D 30/504 (2025.01); H10D 30/506 (2025.01); H10D 30/507 (2025.01); H10D 30/508 (2025.01); H10D 30/509 (2025.01); H10D 30/6211 (2025.01); H10D 30/6217 (2025.01); H10D 30/6219 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/021 (2025.01); H10D 64/514 (2025.01); H10D 64/516 (2025.01); H10D 64/517 (2025.01); H10D 64/518 (2025.01); H10D 64/681 (2025.01); H10D 64/683 (2025.01); H10D 64/685 (2025.01); H10D 64/691 (2025.01); H10D 84/0142 (2025.01); H10D 84/0144 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10W 20/0698 (2026.01);
Abstract

A semiconductor device includes a semiconductor substrate and a field effect transistor disposed on the semiconductor substrate. The field effect transistor includes a vertical fin defining a longitudinal length along a first axis, a width along a second axis and a vertical height along a third axis. The vertical fin includes source and drain regions separated by a gate region and a gate structure over the gate region. The gate structure includes a dipole layer and a gate electrode layer over the dipole layer. A first longitudinal section of the gate structure includes the dipole layer and a second longitudinal section of the gate structure is devoid of the dipole layer.


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