The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Dec. 06, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Bradley Russell Bitz, Meridian, ID (US);

David R. Christianson, Meridian, ID (US);

Travis Michael Jensen, Boise, ID (US);

Kimball Davis Lowry, Boise, ID (US);

Joao Elmiro Chaves, Middleton, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/14 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H05K 1/144 (2013.01); H05K 1/0203 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10734 (2013.01); H05K 2201/10984 (2013.01);
Abstract

A method and an electronic system assembly that includes a first circuit substrate having a surface, wherein the surface has a two-dimensional area defined in a first dimension and a second dimension; a plurality of first semiconductor chip packages mounted on and electrically coupled to the surface; a plurality of second circuit substrates positioned over the surface, wherein each first semiconductor chip package is arranged between the surface and a respective second circuit substrate in a third dimension; a plurality of conductive interconnect structures that extend in the third dimension, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups, and wherein each interconnect group connects a different second circuit substrate to the first circuit substrate; and a plurality of second semiconductor chip packages, wherein each second semiconductor chip package is mounted and electrically coupled to a respective second circuit substrate.


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