The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Jan. 05, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Min-Shin Wu, Hsinchu, TW;

Meng-Sheng Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/18 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 17/16 (2006.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 17/16 (2013.01);
Abstract

A memory circuit may comprise a memory array comprising a plurality of memory cells, an input/output (I/O) circuit, and a power management circuit. The I/O circuit can be operatively coupled to the memory array and configured to read or write each of the memory cells. The power management circuit can be operatively coupled to the memory array and the I/O circuit. The power management circuit can be configured to provide a first gate control signal and a second gate control signal based on a received first supply voltage and a received second supply voltage. The first supply voltage can be substantially higher than two times the second supply voltage.


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