The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2026
Filed:
Nov. 09, 2023
Kepler Computing Inc., San Francisco, CA (US);
Rajeev Kumar Dokania, Beaverton, OR (US);
Erik Unterborn, Cary, NC (US);
Biswajeet Guha, Hillsboro, OR (US);
Pramod Kolar, Cary, NC (US);
Mustansir Yunus Mukadam, Seattle, WA (US);
Darshak Doshi, Sunnyside, CA (US);
Tanay Gosavi, Portland, OR (US);
Amrita Mathuriya, Portland, OR (US);
Debo Olaosebikan, San Francisco, CA (US);
Sasikanth Manipatruni, Portland, OR (US);
Kepler Computing Inc., San Francisco, CA (US);
Abstract
Described herein is a method and apparatus to reduce electric displacement and polarization target for a memory bit-cell. In at least one embodiment, electric displacement and polarization target for non-linear polar material based memory bit-cells is reduced by re-architecting the memory. In at least one embodiment, memory is architected to reduce electric displacement and polarization target by reducing capacitance on sense line or bit-line for bit-cell being accessed or written to. In at least one embodiment, memory arrays are actively split into two or more sub-arrays and routing capacitance is reduced, which in turn reduces capacitance on sense line or bit-line.