The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Jan. 04, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Bei-Shing Lien, Hsinchu, TW;

Szu-Lin Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/46 (2006.01); G05F 1/567 (2006.01); G05F 1/575 (2006.01); G05F 3/26 (2006.01);
U.S. Cl.
CPC ...
G05F 1/468 (2013.01); G05F 1/567 (2013.01); G05F 1/575 (2013.01); G05F 3/262 (2013.01);
Abstract

An integrated circuit includes a first temperature-sensitive device having a first stacked gate device formed and a second stacked gate device, and a second temperature-sensitive device having a third stacked gate device. The first temperature-sensitive device is configured to generate a first voltage which monotonically increases with an absolute temperature. The second temperature-sensitive device is configured to generate a second voltage which monotonically decreases with the absolute temperature. The integrated circuit also includes an output terminal configured to generate a reference voltage which is based on the first voltage from the first temperature-sensitive device and the second voltage from the second temperature-sensitive device. Each of the first stacked gate device, the second stacked gate device, and the third stacked gate device is formed with a first group of field-effect transistors stacked together.


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