Semiconductor chip package with through electrode configuration under recessed connection pad

Abstract

A semiconductor package includes a first semiconductor chip including a first substrate having a front surface and a rear surface, a first insulating layer on the rear surface, a recess portion extending into the first substrate through the first insulating layer, a protective insulating layer extending along an inner side surface and a bottom surface of the recess portion, a through electrode extending from the front surface through the bottom surface of the recess portion and the protective insulating layer, and a first connection pad contacting the through electrode in the recess portion, and surrounded by the protective insulating layer, the first semiconductor chip having a flat upper surface defined by upper surfaces of the first insulating layer, the protective insulating layer, the first connection pad; and a second semiconductor chip disposed on the upper surface of the first semiconductor chip.