The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

May. 05, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hong-Chih Chen, Changhua County, TW;

Fu-Hsiang Su, Zhubei city, TW;

Yu-San Chien, Hsinchu city, TW;

Shih-Hsun Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/85 (2025.01); H01L 21/28 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/85 (2025.01); H01L 21/28123 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01);
Abstract

A method for forming a semiconductor structure is provided. The method includes forming a first active region, forming an interlayer dielectric layer over a source/drain region of the first active region, forming a gate stack to surround the channel region of the first active region, and etching the gate stack and the interlayer dielectric layer to form a cutting trench. The cutting trench includes a first portion extending into the gate stack and a second portion extending into the interlayer dielectric layer. A first width of the first portion of the cutting trench is different than a second width of the second portion of the cutting trench in a direction parallel to a longitudinal axis of the gate stack. The method also includes forming a gate cutting structure in the cutting trench.


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