The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

May. 16, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Lung Tung, Kaohsiung City, TW;

Xiaodong Wang, Hsinchu City, TW;

Jhon-Jhy Liaw, Zhudong Township, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first well region, a second well region, a third well region, and a fourth well region. The semiconductor structure includes a dielectric wall structure formed over a boundary of the first well region and the second well region and longitudinally oriented along a first direction and first channel structures, second channel structures, third channel structures, and fourth channel structures vertically suspended. In addition, the first channel structures are attached to a first sidewall surface of the dielectric wall structure, and the second channel structures are attached to a second sidewall surface of the dielectric wall structure. Furthermore, the second channel structures have a second width in the second direction, the third channel structures have a third width in the second direction, and the second width is greater than the third width.


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