The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Apr. 22, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

An-Hung Tai, Hsinchu, TW;

Chia-Wei Chen, Hsinchu, TW;

Shih-Hang Chiu, Taichung City, TW;

Yu-Hong Lu, Hsinchu City, TW;

Hui-Chi Chen, Zhudong Township, TW;

Kuo-Feng Yu, Zhudong Township, TW;

Jian-Hao Chen, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 84/0184 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01);
Abstract

In a method of manufacturing a semiconductor device, a lower conductive layer is formed in an opening formed in a dielectric layer, and the lower conductive layer is recessed to form a space. A blanket conductive layer is formed over the recessed lower conductive layer in the space, a sidewall of the space and an upper surface of the dielectric layer. Part of the blanket conductive layer formed on the sidewall of the space and the upper surface of the dielectric layer is removed, thereby forming an upper conductive layer on the lower conductive layer, and a cap insulating layer is formed over the upper conductive layer in the space. The blanket conductive layer is formed by physical vapor deposition.


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