The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Jan. 05, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Meng-Sheng Chang, Hsinchu, TW;

Chia-En Huang, Hsinchu, TW;

Yih Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 20/25 (2023.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H10W 42/40 (2026.01);
U.S. Cl.
CPC ...
H10B 20/25 (2023.02); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H10W 42/40 (2026.01);
Abstract

A memory device includes an array having a plurality of one-time-programmable (OTP) memory cells on a side of a substrate, a plurality of word lines (WLs), a plurality of bit lines (BLs), and a plurality of control gate (CG) lines. Each of the OTP memory cells includes a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first and the second fuse resistors are connected to a corresponding one of the BLs, while the first and the second transistors are respectively gated by a first one and a second one of the CG lines. The first transistor, the second transistor, the first fuse resistor, and the second fuse resistor are respectively formed in a first one, a second one, a third one, and a fourth one of a plurality of metallization layers disposed on the side of the substrate.


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