The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

May. 10, 2022
Applicant:

Microchip Technology Inc., Chandler, AZ (US);

Inventors:

Jonathan W. Greene, Palo Alto, CA (US);

Gabriel Barajas, Mountain View, CA (US);

Fei Li, San Jose, CA (US);

Hassan Hassan, Waterloo, CA;

James Sumit Tandon, Fremont, CA (US);

Assignee:

Microchip Technology Inc., Chandler, AZ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/347 (2020.01);
U.S. Cl.
CPC ...
G06F 30/347 (2020.01);
Abstract

A method and apparatus for estimating signal related delays in a PLD design is disclosed. The PLD design is modeled in relation to one or more stages, each of the stages including a driver and one or more receivers coupled to the driver with a wiring tree. The modeling is based on a selected set of parameters that include: slope related delays associated with the driver; a delay related to a layout of the wiring tree; and a parameter related to a slope transfer from a previous driver input. A predetermined set of values for each of the selected parameters are accessed; the estimated signal related delays are computed for each of the modeled stages; and are written to a computer-readable storage medium.


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