The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Aug. 08, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Jiun Yi Wu, Zhongli City, TW;

Chen-Hua Yu, Hsinchu, TW;

Chung-Shi Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49833 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/31 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/562 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01);
Abstract

In an embodiment, a method for manufacturing a semiconductor device includes forming a redistribution structure on a carrier substrate, connecting a plurality of core substrates physically and electrically to the redistribution structure with a first anisotropic conductive film, the first anisotropic conductive film including a dielectric material and conductive particles, and pressing the plurality of core substrates and the redistribution structure together to form conductive paths between the plurality of core substrates and the redistribution structure with the conductive particles in the first anisotropic conductive film. The method also includes encapsulating the plurality of core substrates with an encapsulant. The method also includes and attaching an integrated circuit package to the redistribution structure, the redistribution structure being between the integrated circuit package and the plurality of core substrates, the integrated circuit package laterally overlapping a first core substrate and a second core substrate of the plurality of core substrates.


Find Patent Forward Citations

Loading…