The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Aug. 08, 2022
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Jeffrey Smith, Clifton Park, NY (US);

Hiroaki Niimi, Cohoes, NY (US);

Kandabara Tapily, Mechanicville, NY (US);

Daniel Chanemougame, Niskayuna, NY (US);

Lars Liebmann, Mechanicville, NY (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 20/00 (2026.01); H10D 62/13 (2025.01); H10W 10/00 (2026.01); H10W 10/17 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10W 20/42 (2026.01); H10D 62/151 (2025.01); H10W 10/014 (2026.01); H10W 10/17 (2026.01); H10W 20/033 (2026.01); H10W 20/057 (2026.01); H10W 20/0698 (2026.01); H10W 20/081 (2026.01);
Abstract

A semiconductor device includes a field-effect transistor (FET) having a source/drain (S/D) structure and an interconnect structure in contact with the S/D structure. The interconnect structure has a barrier film at a surface of the interconnect structure separating the interconnect structure from materials surrounding the interconnect structure. A first portion of the barrier film covers a first interface between the interconnect structure and the S/D structure. A second portion of the barrier film covers a second interface between the interconnect structure and dielectric materials adjacent to the interconnect structure. The first portion of the barrier film is thicker than the second portion of the barrier film.


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