The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Aug. 01, 2022
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Aniket Patil, San Diego, CA (US);

Hong Bok We, San Diego, CA (US);

Joan Rey Villarba Buot, Escondido, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 86/85 (2025.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/654 (2026.01); H10W 70/685 (2026.01); H10W 72/00 (2026.01); H10W 72/29 (2026.01); H10W 72/90 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10D 86/85 (2025.01); H10W 70/611 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10W 70/05 (2026.01); H10W 70/65 (2026.01); H10W 70/654 (2026.01); H10W 72/019 (2026.01); H10W 72/072 (2026.01); H10W 72/073 (2026.01); H10W 72/29 (2026.01); H10W 72/90 (2026.01); H10W 72/9223 (2026.01); H10W 72/923 (2026.01); H10W 72/934 (2026.01); H10W 72/9415 (2026.01); H10W 72/9445 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

Deep trench capacitors (DTCs) employing bypass metal trace signal routing supporting signal bypass routing, and related integrated circuit (IC) packages and fabrication methods are disclosed. The DTC includes an outer metallization layer (e.g., a redistribution layer (RDL)) to provide an external interface to the DTC. In exemplary aspects, to make available signal routes that can extend through a DTC, an outer metallization layer of the DTC includes additional metal interconnects. These additional metal interconnects are not coupled the capacitors in the DTC. These additional metal interconnects are interconnected to each other by metal traces (e.g., metal lines) in the outer metallization layer of the DTC to provide bypass signal routes through the DTC. This is opposed to signal paths in a package substrate in which the DTC is coupled or embedded having to be routed around the DTC in the package substrate.


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