The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Jan. 18, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Ming-Huei Lin, New Taipei, TW;

Haining Yang, San Diego, CA (US);

Junjing Bao, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/00 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H01L 21/3115 (2006.01);
U.S. Cl.
CPC ...
H10D 84/853 (2025.01); H10D 84/0172 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H01L 21/31155 (2013.01);
Abstract

A fin field effect transistor (FinFET) is described. The FinFET includes a substrate and a shallow trench isolation (STI) region on the substrate. The FinFET also includes a first fin structure on the substrate and extending through the STI region. The FinFET further includes a second fin structure on the substrate and extending through the STI region. The FinFET also includes a metal gate on the STI region, on the first fin structure, and on the second fin structure. The metal gate is composed of a first sub-metal gate cut line filled with a first stressor material, and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.


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