The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

May. 19, 2023
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventor:

Jeffrey Smith, Clifton Park, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2026.01); H10D 84/85 (2025.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 90/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/01 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/021 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/856 (2025.01); H10W 90/00 (2026.01); H10W 72/0198 (2026.01); H10W 72/07331 (2026.01); H10W 72/323 (2026.01); H10W 72/353 (2026.01); H10W 72/355 (2026.01); H10W 90/20 (2026.01); H10W 90/297 (2026.01); H10W 90/732 (2026.01);
Abstract

A method of manufacturing a semiconductor device includes forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material that is etch selective to the first semiconductor material. Fin structures are formed from the stack. The fin structures include channel structures formed of the first semiconductor material. The channel structures have opposing ends that are uncovered. Sidewall constraints are formed at the opposing ends of the channel structures. Each pair of the sidewall constraints laterally bounds a respective source/drain (S/D) region at a respective end of the channel structures while having a respective top opening for accessing the respective S/D region. S/D structures are formed on the opposing ends of the channel structures by epitaxially growing a third semiconductor material between each pair of the sidewall constraints.


Find Patent Forward Citations

Quick Actions:

Smith, Jeffrey. (2026). Method of forming confined growth s/d contact defined by sidewall constraints with selective deposition of inner spacer for cfet (U.S. Patent No. 12628411). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12628411

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