The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2026
Filed:
May. 05, 2023
Qualcomm Incorporated, San Diego, CA (US);
Peijie Feng, San Diego, CA (US);
Yan Sun, San Diego, CA (US);
Shreesh Narasimha, Charlotte, NC (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Enhanced-shaped extension region for gate-all-around (GAA) field-effect transistor (FET) devices and related fabrication methods are disclosed. The GAA FET device includes an extension region of semiconductor material coupled from the respective channel to the source/drain region to facilitate forming a conductive channel between the source and the drain regions when the GAA FET device is activated. The area of the extension region between the source/drain regions and the channel forms a series resistance between source/drain regions and the channel. To reduce channel parasitic resistance, the extension region of the GAA FET device has an enhanced extension portion that has an extended height orthogonal to the channel direction. The extension region with its enhanced extension portion has reduced resistance as compared to an extension region not containing the enhanced extension portion, thus reducing channel parasitic resistance of the GAA FET device for improved performance.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile