The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2026
Filed:
Jun. 22, 2023
Qualcomm Incorporated, San Diego, CA (US);
Shreesh Narasimha, Charlotte, NC (US);
Yan Sun, San Diego, CA (US);
Peijie Feng, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
A gate-all-around (GAA) field effect transistor (FET) device, and related fabrication methods are disclosed. The GAA FET device includes P-type semiconductor PFET(s) and N-type semiconductor NFET(s) having channels with different crystalline orientation through a substrate. The GAA PFET(s) includes a channel structure of a first type of crystalline orientation (e.g., <110> or <111>) and the GAA NFET(s) include a channel structure of a second type of crystalline orientation (e.g., <100>) different from the first type of crystalline orientation of the GAA PFET(s). The different crystalline orientation channels improve the balance of carrier mobility for both carrier types (i.e., P-type and N-type) of GAA FETs in the GAA FET device. In one aspect, the different crystalline orientation channels are provided through a substrate to increase and/or balance carrier mobility between GAA PFET(s) and NFET(s) to achieve a more balanced drive strength between these types of transistors.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile