The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2026
Filed:
Sep. 23, 2022
Synopsys, Inc, Mountain View, CA (US);
Balkrishna Ramchandra Rashingkar, Sunnyvale, CA (US);
Andrew Saunders, Reading, GB;
Douglas Chang, San Jose, CA (US);
Jeffrey Jude Loescher, Portland, OR (US);
Oliver Werner Kozber, Beaverton, OR (US);
Liang Tao, Campbell, CA (US);
Soumitra Majumder, Kolkata, IN;
Colin Williams, Cary, NC (US);
Synopsys, Inc., Sunnyvale, CA (US);
Abstract
Design metrics from the physical design of an integrated circuit are made available to the front end designer. Physical design metrics are computed for sub-circuits from the physical design of an integrated circuit. Examples of physical design metrics include metrics for timing, congestion, power consumption and other metrics that depend on physical aspects of the circuit. Correspondence between the sub-circuits and register transfer level (RTL) source elements from RTL source code for the integrated circuit are determined. Examples of RTL source elements include individual lines of RTL source code, modules in the RTL source code, and user-defined constructs in the RTL source code. For different RTL source elements, the physical design metrics for the corresponding sub-circuits are aggregated. These aggregated physical design metrics, including the associations to the corresponding RTL source elements, are made available to users, for example front end designers.