The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Mar. 03, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Thomas Wagner, Regelsbach, DE;

Abdallah Bacha, Munich, DE;

Vishnu Prasad, Munich, DE;

Mohan Prashanth Javare Gowda, Ottobrunn, DE;

Bernd Waidhas, Pettendorf, DE;

Sonja Koller, Bavaria, DE;

Eduardo De Mesa, Munich, DE;

Jan Proschwitz, Riesa SN, DE;

Lizabeth Keser, San Diego, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/5389 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/32225 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.


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