The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Sep. 30, 2022
Applicant:

Zhuhai Access Semiconductor Co., Ltd, Guangdong, CN;

Inventors:

Xianming Chen, Guangdong, CN;

Jindong Feng, Guangdong, CN;

Benxia Huang, Guangdong, CN;

Yejie Hong, Guangdong, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10W 40/00 (2026.01); H10W 40/22 (2026.01); H10W 40/25 (2026.01); H10W 70/05 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01);
U.S. Cl.
CPC ...
H10W 70/614 (2026.01); H10W 40/037 (2026.01); H10W 40/228 (2026.01); H10W 40/258 (2026.01); H10W 70/05 (2026.01); H10W 70/095 (2026.01); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10W 72/30 (2026.01); H10W 72/874 (2026.01);
Abstract

A two-sided interconnected embedded chip packaging structure includes a first insulating layer and a second insulating layer. The first insulating layer includes a first conductive copper column layer penetrating through the first insulating layer in a height direction and a first chip located between adjacent first conductive copper columns, and the first chip is attached to the inside of the lower surface of the first insulating layer. The second insulating layer includes a first conductive wire layer and a heat radiation copper surface which are located in the upper surface of the second insulating layer, the first conductive wire layer is provided with a second conductive copper column layer, the first conductive copper column layer is connected with the first conductive wire layer, and the heat radiation copper surface is connected with the reverse side of the first chip.


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