The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Feb. 21, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Toyohiro Aoki, Yokohama, JP;

Katsuyuki Sakuma, Fishkill, NY (US);

Hiroyuki Mori, Yasu, JP;

Koki Nakamura, Kawasaki, JP;

Takashi Hisada, Hachiouji, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/05 (2026.01); H10P 76/20 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/093 (2026.01); H10W 90/701 (2026.01); H10P 76/204 (2026.01); H10W 72/01223 (2026.01); H10W 72/227 (2026.01); H10W 72/241 (2026.01); H10W 72/9415 (2026.01);
Abstract

Methods, systems, and structures relating to flip-chip bonding are described. A processor can determine a plurality of target solder volumes to be deposited on a plurality of pads on a surface of a substrate. The plurality of target solder volumes can be variable among the plurality of pads. The processor can determine different thicknesses of different portions of a layer of resist to be deposited across the surface of the substrate. The different thicknesses can define a plurality of solder resist openings having sizes that comply with the plurality of target solder volumes.


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