The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

May. 09, 2023
Applicant:

Nexperia B.v., Nijmegen, NL;

Inventors:

Steven Peake, Manchester, GB;

MD Imran Siddiqui, Manchester, GB;

Assignee:

Nexperia B.V., Nijmegen, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 21/763 (2006.01); H10D 30/01 (2025.01); H10D 30/66 (2025.01); H10D 64/00 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H01L 22/26 (2013.01); H01L 21/02238 (2013.01); H01L 21/32137 (2013.01); H01L 21/763 (2013.01); H10D 30/0297 (2025.01); H10D 30/668 (2025.01); H10D 64/01 (2025.01); H10D 64/117 (2025.01);
Abstract

A method of creating a vertical semiconductor device, the method includes the steps of performing a LOCal Oxidation of Silicon, LOCOS, process in a vertical trench of a semiconductor material so that oxide material is formed inside the vertical trench, and ledges are formed by the oxide material, inside the vertical trench, as a result of the LOCOS process, so that a lower region of reduced lateral distance is formed between the oxide material, at a base of the trench, depositing the trench with polysilicon and etching the polysilicon downward up to the oxide material using interferometric end point detection, so that polysilicon remains in the lower region.


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