The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Aug. 31, 2022
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Yihang Liu, Santa Clara, CA (US);

Xiaochen Zhu, Milpitas, CA (US);

Lito De La Rama, San Jose, CA (US);

Feng Gao, Union City, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/16 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3495 (2013.01); G11C 16/0433 (2013.01); G11C 16/0483 (2013.01); G11C 16/16 (2013.01); G11C 16/3445 (2013.01);
Abstract

An apparatus is provided that includes a block of memory cells having a NAND string that includes a first select transistor, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a first count of a number of times that the block of memory cells previously has been programmed and erased, determining based on the first count a first drain-to-gate voltage of the first select transistor, wherein the first drain-to-gate voltage is configured to cause the first select transistor to generate a first gate-induced drain leakage current, and applying a first erase pulse to the first select transistor based on the determined first drain-to-gate voltage.


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