The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2026
Filed:
Nov. 30, 2022
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Frederick Atadana, Hillsboro, OR (US);
Jean Bosco Kana Kana, Chandler, AZ (US);
Shripad Gokhale, Gilbert, AZ (US);
Xavier F. Brun, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/15 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H10W 40/25 (2026.01); H10W 70/60 (2026.01); H10W 70/63 (2026.01); H10W 70/692 (2026.01); H10W 90/00 (2026.01); H10W 99/00 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 40/259 (2026.01); H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 70/692 (2026.01); H10W 90/00 (2026.01); H10W 90/401 (2026.01); H10W 99/00 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract
Disclosed herein are microelectronics package architectures utilizing glass layers and methods of manufacturing the same. The microelectronics packages may include a silicon layer, dies, and a glass layer. The silicon layer may include vias. The dies may be in electrical communication with vias. The glass layer may include interconnects in electrical communication with the vias.