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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12615817 B1

PDFFull Text
Date of Patent:
Apr. 28, 2026

Filed:

Jun. 27, 2023

Stacked fet with low parasitic-capacitance gate

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Brent A. Anderson, Jericho, VT (US);

Junli Wang, Slingerlands, NY (US);

Jay William Strane, Wappinger Falls, NY (US);

Albert M. Chu, Nashua, NH (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorney:

Samuel A. Waldbaum

Primary Examiner:

David C Spalla

Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/115 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 84/83 (2025.01);
Abstract

A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.

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