The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

May. 31, 2024
Applicant:

Sandisk Technologies Inc., Milpitas, CA (US);

Inventors:

Abu Naser Zainuddin, San Ramon, CA (US);

Xuan Tian, Shanghai, CN;

Jiahui Yuan, Fremont, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/102 (2013.01); G11C 16/3404 (2013.01);
Abstract

A memory apparatus has memory cells grouped into a first plane and a second plane and are configured to retain a threshold voltage corresponding to data states. A control means applies one of a plurality of program pulses followed by a verify pulse of at least one verify voltage to a group of the memory cells of the first plane and the second plane during one of a plurality of program-verify iterations. The control means terminates programming of one of the first plane or the second plane prior to completing programming of the one of the first plane or the second plane in response to determining the one of first plane or the second plane programs slower. The terminated plane is additionally determined based on sensing the threshold voltage of the memory cells for a long sense time longer than used during the one of the plurality of program-verify iterations.


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