The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2026
Filed:
Jun. 01, 2024
Applicant:
Sandisk Technologies, Inc., Milpitas, CA (US);
Inventors:
Wei Cao, Fremont, CA (US);
Xiang Yang, Santa Clara, CA (US);
Jiahui Yuan, Fremont, CA (US);
Deepanshu Dutta, Fremont, CA (US);
Assignee:
Sandisk Technologies, Inc., Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); H01L 25/065 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06562 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract
The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells are programmed according to a one bit per memory cell (SLC) programming scheme that includes an erased data state and a programmed data state. The memory cells in both the erased data state and in the programmed data state have threshold voltages Vt that are less than 0 V.