The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Jun. 07, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Naveen Kumar, Bangalore, IN;

Gururaj Shamanna, Austin, TX (US);

Jagadeesh Chandra Salaka, Bengaluru, IN;

Purna Chandra Nayak, Bangalore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01);
Abstract

An apparatus, system, and method for improved replica bit line (RBL) operation are provided. An memory control circuit can include an RBL including a plurality of replica bit cells (RBCs) electrically coupled in series, a timer and control logic circuit situated to receive an output of the RBL, and a first multiplexer electrically coupled between the RBL and the timer and control logic circuit, the first multiplexer configured to set a replica word line (RWL) that controls, based on a state of select lines input into the first multiplexer and input provided by the timer and control logic, which of the RBCs is active.


Find Patent Forward Citations

Kumar, Naveen. (2026). Variation tolerant reconfigurable replica bitline circuits (U.S. Patent No. 12614586). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12614586

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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