The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2026
Filed:
May. 04, 2022
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); G06N 3/04 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); G06N 3/04 (2013.01); H01L 24/16 (2013.01); H01L 25/105 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1435 (2013.01);
Abstract
An in-memory computing circuit is provided. The in-memory computing circuit includes a core die, a plurality of conductive pillars, and a plurality of memory dies. The plurality of memory dies are coupled to the core die through the plurality of conductive pillars and are configured to implement computing operation. The plurality of memory dies includes at least one of the memory dies disposed on a bottommost memory die of the plurality of memory dies. The plurality of memory dies receives an input data from the core die through a common input terminal of the core die.