The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Dec. 15, 2020
Applicant:

Wuhan Xinxin Semiconductor Manufacturing Co., Ltd., Wuhan, CN;

Inventors:

Tian Zeng, Wuhan, CN;

Di Zhan, Wuhan, CN;

Tianjian Liu, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/768 (2006.01); H10F 39/00 (2025.01);
U.S. Cl.
CPC ...
H10F 39/026 (2025.01); H01L 21/486 (2013.01); H01L 21/76898 (2013.01); H10F 39/018 (2025.01); H10F 39/809 (2025.01); H10F 39/811 (2025.01);
Abstract

A method of manufacturing a semiconductor device includes: providing bonded first and second wafers; forming a patterned insulating layer on the second substrate, the patterned insulating layer having first holes and dummy holes both exposing the second substrate; forming a protective layer, which fills a partial depth of the dummy holes and covers side surfaces of the first holes; forming through-silicon vias (TSVs); and forming a second metal layer including an interconnect metal layer and a dummy metal layer, the interconnect metal layer filling the TSVs and electrically connected to the first metal layer, the dummy metal layer filling the dummy holes. The formation of the dummy metal layer is integrated in the TSV process and is therefore done without using any additional process or adding additional cost to enable uniform pattern density (e.g., metal density) across the surface of the second wafer and enhanced CMP uniformity.


Find Patent Forward Citations

Zeng, Tian. (2026). Semiconductor device and manufacturing method therefor, and chip bonding structure (U.S. Patent No. 12610632). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12610632

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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