Sram with improved program and sensing margin for scaled nanosheet devices

Abstract

An integrated circuit structure includes a memory cell and multiple transistors therein. The multiple transistors are formed using channels including a stack having alternating layers of conductive semiconductor material and layers of other material that are insulative. Two or more of the multiple transistors have a same number of layers of the conductive semiconductor material in corresponding channel regions but have different numbers of active layers and inactive layers of the conductive semiconductor material. An active layer is a layer forming a channel in the channel region that is electrically coupled to S/D regions in a corresponding transistor, while a floating layer is a layer in the channel region electrically isolated from the S/D regions in the corresponding transistor. Methods for forming the integrated circuit structure are disclosed.